Written by David Leach, Software Architect at NXP Semiconductor and member of the Zephyr Technical Steering Committee Last month, the Zephyr Project announced the release of Zephyr RTOS 2.1. A…
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This blog originally ran on the Antmicro website. For more Zephyr development tips and articles, please visit their blog. While much of the focus for the recent developments in AI has…
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By Maureen Helm, Chair of the Zephyr Project Technical Steering Committee The Zephyr community converges every year at the Embedded Linux Conference Europe, and 2019 was no exception. This year…
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This blog originally ran on the Antmicro website. For more Zephyr development tips and articles, please visit their blog. Solving problems that require real-time calculations and precise control typically calls for…
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Written by Ivo Clarysse, CTO at Blue Clover Devices This blog previously ran on the Blue Clover Devices website. You can view the website here. IOT OS LANDSCAPE These days there’s…
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Amy Occhialino is the Chair of the Zephyr Project Governing Board and Director of Software Engineering at Intel. She has more than 20 years experience in technology and has recently…
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This blog originally ran on the Antmicro website. For more Zephyr development tips and articles, please visit their blog. Antmicro’s open source simulation framework, Renode, was built to enable simulating real-life scenarios…
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Written by Nicolas Pitre, Senior Software Engineer at BayLibre SiFive HiFive Unleashed Board This blog post originally ran on the BayLibre website last month. For more details about BayLibre, visit https://baylibre.com/.…
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Written by Ioannis Glaropoulos, Software System Architect at Nordic Semiconductor and active member of the Zephyr Technical Steering Committee Last month, the Zephyr Project announced the release of Zephyr RTOS…
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This blog originally appeared on the Antmicro blog. The UltraScale+, a high-performance FPGA SoC designed for heterogeneous processing with 4 Cortex-A53 cores and 2 Cortex-R5 cores, is often used in Antmicro’s…
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